ASIC Design
Developing high quality RTL is challenging because the chip needs to be low on area and power consumption and at the same time provide adequate performance. To overcome this, we leverage dozens of years’ experience of our team and follow stringent design checklist.
Area Of Expertise
Micro-Architecture
RTL Development & QC Checks e.g. Lint, CDC
Design Timing Constraints
Low Power Design Implementation & UPF Checks
Logical Equivalance check
Synthesis and STA
AMBA AXI, AHB, APB, Protocols, OCP, ARM Subsystem
Audio, Display, Camera, PCIe, Ethernet, USB Subsystems
PCIe, Ethernet, OCP, WLAN, CPU domain
