User Defined register implementation for all concern control bits. On-chip Clock insertion for respective clock domain, TAP controller and Boundary scan insertion,Test-Pinmuxing

MBIST insertion at block/TOP level, Scan insertion/LBIST insertion, IOwrapper insertion for each DFT blocks, compression/decompression insertion

Expertize in different format of pattern generation i.e. Verilog, ASCII, different ATE format, Cell-aware pattern generation, Power-aware pattern generation, Pattern re-targeting ,Zero-delay as well as timing verification across different SDF corners, ATE pattern generation, and Silicon debug of failing patterns

Expertize in MBIST verification for Block level as well as Full-Chip level, MBIST verification for repairable and nonrepairable memories.

No-timing simulation & debug, timing simulation & debug across different SDF corners, ATE pattern generation for MBIST controllers, Silicon debug of failing patterns

Expertise in BSCAN verification with respect to IEEE 1149.1 & IEE1149.6 protocol

Simulation debug without and with SDF across different PVT corners, ATE patterns generation for different requirements and silicon debug

Expertize in ATE test program development for Digital domain, Analog domain, Mixed signal, RF domain, Program development for engineering evaluation as well as production support

ATE program development and debug support on multiple tester platform, Multi Site program development, program conversion from one platform to another platform, PVT characterization

Expertize in Load boards, Handler Interface Board, DUT Interface Board-TE Expertize in Probe Card, Probe Interface board, Device characterization board, burn-In board Expertize in different kind of BGA, Leadframe, Hermetic package through our partners